Quickfilter QF4A512-PA Specifiche

DATA SHEET QF4A512 4-Channel Programmable Signal Converter (PSC) PRODUCTION DATA is current as of the publication date. Rev D4, Dec 07 Produc

DATA SHEET QF4A512 Rev D4, Dec 07 10 www.quickfiltertech.com 9 DVDD18 Power +1.8V DC Power (Digital) 10 DGND Ground Digital Ground 11 DGND

DATA SHEET QF4A512 Rev D4, Dec 07 11 www.quickfiltertech.com 3. GENERAL DESCRIPTION Figure 1. Functional Block Diagram 3.1 Analog Front End (

DATA SHEET QF4A512 Rev D4, Dec 07 12 www.quickfiltertech.com The purpose of the CIH stage is droop recovery to compensate for the frequency re

DATA SHEET QF4A512 Rev D4, Dec 07 13 www.quickfiltertech.com Within EEPROM, 128 bytes of user space are provided for storing application-speci

DATA SHEET QF4A512 Rev D4, Dec 07 14 www.quickfiltertech.com 5. STARTUP The behavior of the QF4A512 during power up or after a reset can be de

DATA SHEET QF4A512 Rev D4, Dec 07 15 www.quickfiltertech.com The sequence of events that occurs after a hardware reset is detailed in the prec

DATA SHEET QF4A512 Rev D4, Dec 07 16 www.quickfiltertech.com Note: The value in the IGC_SEQADDR registers can set in two ways. By default, if

DATA SHEET QF4A512 Rev D4, Dec 07 17 www.quickfiltertech.com 6. ANALOG FRONT END (AFE) 6.1 Configurable parameters The following items are con

DATA SHEET QF4A512 Rev D4, Dec 07 18 www.quickfiltertech.com 6.4 Input Voltage Levels Ideally the maximum input voltage to the QF4A512 should

DATA SHEET QF4A512 Rev D4, Dec 07 19 www.quickfiltertech.com 7. ANALOG TO DIGITAL CONVERTER 7.1 Overview The ADC has a pipeline architecture t

DATA SHEET QF4A512 Rev D4, Dec 07 2 www.quickfiltertech.com TABLE OF CONTENTS 1. SPECIFICATIONS ...

DATA SHEET QF4A512 Rev D4, Dec 07 20 www.quickfiltertech.com The aggregate bandwidth is the total bandwidth available to all active channels.

DATA SHEET QF4A512 Rev D4, Dec 07 21 www.quickfiltertech.com 7.9 User (System-level) Calibration Overall system level performance can be impro

DATA SHEET QF4A512 Rev D4, Dec 07 22 www.quickfiltertech.com 8. FIR FILTERS 8.1 FIR Overview Each channel features a 512-tap FIR which is used

DATA SHEET QF4A512 Rev D4, Dec 07 23 www.quickfiltertech.com 8.3 FIR Latency There will be a delay introduced to the signal as it passes throu

DATA SHEET QF4A512 Rev D4, Dec 07 24 www.quickfiltertech.com which clocks are derived to drive the FIR filters, the ADC and the analog front e

DATA SHEET QF4A512 Rev D4, Dec 07 25 www.quickfiltertech.com The QF4A512 is designed to interface directly with the serial peripheral interfac

DATA SHEET QF4A512 Rev D4, Dec 07 26 www.quickfiltertech.com Note, this data applies to SO and SI depending whether it is being read or writte

DATA SHEET QF4A512 Rev D4, Dec 07 27 www.quickfiltertech.com 10.3 Run Mode By setting the run_mode bit to 1 the QF4A512 is in Run mode, and wi

DATA SHEET QF4A512 Rev D4, Dec 07 28 www.quickfiltertech.com Table 13. Output Data, MSB, SD0 (00h-FFh) D23 D22 D21 D20 D19 D18 D17 D16 PAR

DATA SHEET QF4A512 Rev D4, Dec 07 29 www.quickfiltertech.com Figure 12. Run Mode Timing, Read and Write Note: Once set by the chip DRDY wi

DATA SHEET QF4A512 Rev D4, Dec 07 3 www.quickfiltertech.com 9. SYSTEM CLOCKS ...

DATA SHEET QF4A512 Rev D4, Dec 07 30 www.quickfiltertech.com In Configure mode 14-bit address words are used. In Run mode 8-bit addressing is

DATA SHEET QF4A512 Rev D4, Dec 07 31 www.quickfiltertech.com 11. EEPROM 11.1 Overview Table 14. EEPROM Memory Map 0F80 User Data (128 bytes)

DATA SHEET QF4A512 Rev D4, Dec 07 32 www.quickfiltertech.com Multi-Byte Transfer Restrictions Reading from EEPROM A contiguous transfer will

DATA SHEET QF4A512 Rev D4, Dec 07 33 www.quickfiltertech.com Alternatively other user-specific information and/or formats can be stored in thi

DATA SHEET QF4A512 Rev D4, Dec 07 34 www.quickfiltertech.com Several registers are designated as “Reserved”. The user may write to these regis

DATA SHEET QF4A512 Rev D4, Dec 07 35 www.quickfiltertech.com 02h FULL_SRST (Global Soft Reset) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B

DATA SHEET QF4A512 Rev D4, Dec 07 36 www.quickfiltertech.com * 0 = default 1 = start transfer Description: Command to start transfer from EEP

DATA SHEET QF4A512 Rev D4, Dec 07 37 www.quickfiltertech.com * 0 = Configure mode. 1 = Run mode Description: In Run mode automatically starts

DATA SHEET QF4A512 Rev D4, Dec 07 38 www.quickfiltertech.com pcg_chN_en *0 = Disabled 1 = Enabled Description: Enables the ADC clock and sys

DATA SHEET QF4A512 Rev D4, Dec 07 39 www.quickfiltertech.com Description: Indicates PLL lock status. ism_pll_lock – AUTO SET, may be reset by

DATA SHEET QF4A512 Rev D4, Dec 07 4 www.quickfiltertech.com 1. SPECIFICATIONS 1.1 Absolute Maximum Ratings Stresses above those listed under A

DATA SHEET QF4A512 Rev D4, Dec 07 40 www.quickfiltertech.com adc_unN * 0 = No underflow. 1 = ADC underflow, out of range, low. Description: In

DATA SHEET QF4A512 Rev D4, Dec 07 41 www.quickfiltertech.com adcclk_rate *00 = PLL clock/2 01 = PLLCLK/4 10 = PLLCLK/8 11 = PLLCLK/16 Descript

DATA SHEET QF4A512 Rev D4, Dec 07 42 www.quickfiltertech.com 1 = Enable Description: Enable address autoincrement. If set, on the next read/wr

DATA SHEET QF4A512 Rev D4, Dec 07 43 www.quickfiltertech.com Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Address 1Bh addr7 addr6 a

DATA SHEET QF4A512 Rev D4, Dec 07 44 www.quickfiltertech.com Address 26h X X X pmux_srst arec_srst spim_rst iIgc_srst pcg_srst *0 = Default 1

DATA SHEET QF4A512 Rev D4, Dec 07 45 www.quickfiltertech.com Run and Status Registers 30h CH1_PGA (Programmable Gain Amplifier Setting, FIR b

DATA SHEET QF4A512 Rev D4, Dec 07 46 www.quickfiltertech.com *0 = No overflow 1 = Overflow Description: FIR, filter 1, input buffer overflow

DATA SHEET QF4A512 Rev D4, Dec 07 47 www.quickfiltertech.com Description: Enable FIR operation, filter 1. fir_0_0_bypass 0 = In-circuit *1 =

DATA SHEET QF4A512 Rev D4, Dec 07 48 www.quickfiltertech.com Address 3Ah X D6 D5 D4 D3 D2 D1 D0 Description: CIC shift value, default; value

DATA SHEET QF4A512 Rev D4, Dec 07 49 www.quickfiltertech.com 3Fh FIR_0_0_CMAX_F1 (Maximum coefficient storage address for f1) Bit 7 Bit 6

DATA SHEET QF4A512 Rev D4, Dec 07 5 www.quickfiltertech.com 1.4 Electrical Characteristics Symbol Parameter (Condition) Min Typ Max Units No

DATA SHEET QF4A512 Rev D4, Dec 07 50 www.quickfiltertech.com fir_0_1_decimf1 Description: Decimation value for f1. Default value = 0, values

DATA SHEET QF4A512 Rev D4, Dec 07 51 www.quickfiltertech.com 4Dh FIR_0_1_NMAX_F2 (Maximum storage address for f2) Bit 7 Bit 6 Bit 5 Bit

DATA SHEET QF4A512 Rev D4, Dec 07 52 www.quickfiltertech.com Description: Soft reset the FIR block, filter 0. fir_0_1_srst *0 = No action 1

DATA SHEET QF4A512 Rev D4, Dec 07 53 www.quickfiltertech.com Default value = 8000 Description: Gain calibration value is written here. 5Ah – 5

DATA SHEET QF4A512 Rev D4, Dec 07 54 www.quickfiltertech.com 1 = Gain calibration Description: Select whether to perform gain or offset calib

DATA SHEET QF4A512 Rev D4, Dec 07 55 www.quickfiltertech.com 100h FIR_0_0_COEF_RAM (Coefficients for G Filter Channel 1, LSB) Bit 7 Bit 6

DATA SHEET QF4A512 Rev D4, Dec 07 56 www.quickfiltertech.com (C1TH1_0 - C1TH1_7): Represents the LSB in half of TAP1 Coefficient Data for Chan

DATA SHEET QF4A512 Rev D4, Dec 07 57 www.quickfiltertech.com 301h FIR_0_1_COEF_RAM (Coefficients for FIR Filter per Channel, Byte 2) Bit 7

DATA SHEET QF4A512 Rev D4, Dec 07 58 www.quickfiltertech.com 1400h FIR_0_1_DATA_RAM (FIR Data Memory, LSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

DATA SHEET QF4A512 Rev D4, Dec 07 59 www.quickfiltertech.com 12.10 Register Listing 00H GLBL_SW (USER REGISTER) ...

DATA SHEET QF4A512 Rev D4, Dec 07 6 www.quickfiltertech.com Differential Input Capacitance 10 pF Differential Input Resistance 4.6

DATA SHEET QF4A512 Rev D4, Dec 07 60 www.quickfiltertech.com 41H FIR_0_0_NMAX_F2 (MAXIMUM STORAGE ADDRESS FOR F2) ...

DATA SHEET QF4A512 Rev D4, Dec 07 61 www.quickfiltertech.com 13. APPLICATION CIRCUITS For more information please see Application note QFAN004

DATA SHEET QF4A512 Rev D4, Dec 07 62 www.quickfiltertech.com 13.2 DC coupled, Single-ended Figure 15. Application Circuit – Single-ended, dc

DATA SHEET QF4A512 Rev D4, Dec 07 63 www.quickfiltertech.com 13.3 AC coupled, Differential Figure 16. Application Circuit – Differential, ac

DATA SHEET QF4A512 Rev D4, Dec 07 64 www.quickfiltertech.com 13.4 DC coupled, Differential Figure 17. Application Circuit – Differential, dc c

DATA SHEET QF4A512 Rev D4, Dec 07 65 www.quickfiltertech.com 14. PACKAGING INFORMATION 7x7x1.4mm, LQFP 32, 0.8 mm Pitch POD (JEDEC)

DATA SHEET QF4A512 Rev D4, Dec 07 66 www.quickfiltertech.com List of Figures FIGURE 1. FUNCTIONAL BLOCK DIAGRAM...

DATA SHEET QF4A512 Rev D4, Dec 07 67 www.quickfiltertech.com The contents of this document are provided in connection wit

DATA SHEET QF4A512 Rev D4, Dec 07 7 www.quickfiltertech.com VOH High-level Output Voltage, DVDD18 = 1.6V, IOH = -100uA 1.4 V VOL Low

DATA SHEET QF4A512 Rev D4, Dec 07 8 www.quickfiltertech.com 1.6 Typical Performance Characteristics Default Conditions: TA = 25 C, VDD18 = 1.

DATA SHEET QF4A512 Rev D4, Dec 07 9 www.quickfiltertech.com 2. PINOUT and PIN DESCRIPTIONS 2.1 Pinout AIN1-1QF4A512 32 LQFP2345678XGND